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JEDEC - Solid State Technology Association: Recent submissions
Now showing items 141-160 of 369
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JEDEC JESD75
Abstract: The purpose of this standard is to provide a pinout standard for dual-die 32-bit logic devices offered in a 96- and 144-ball grid array package for uniformity, multiplicity of sources, elimination of confusion, ease of ...Subject(s) : 32-Bit Logic Functions , Ball Grid Array Pinouts , LFBGA , Low Profile , -
JEDEC JESD22-A110D
Abstract: The Highly-Accelerated Temperature and Humidity Stress Test is performed for the purpose of evaluating the reliability of non-hermetic packaged solid-state devices in humid environments. It employs severe conditions of ... -
JEDEC JESD22-B103B
Abstract: This method is intended to evaluate component(s) for use in electrical equipment. It is intended to determine the ability of the component(s) to withstand moderate to severe vibration as a result of motion produced by ... -
JEDEC JESD217
Abstract: This publication provides an overview of solder void types, outlines current metrologies and test methods used for pre-SMPT solder void characterization and potential limitations, and prescribes sampling strategy for data ... -
JEDEC JESD12
Abstract: The purpose of these benchmarks is to provide a common set of high level functions which serve as vehicles for comparing the performance of gate arrays implemented in any technology using any internal structure. These ...Subject(s) : Cell Based - Integrated Circuits , Gate Array - Performance , -
JEDEC JESD8-2
Abstract: This Addendum No. 2 to JEDEC Standard No. 8 provides standard operating voltage and interface levels that can be used by designers and application engineers as they develop and introduce new products. Covers the ECL logic ...Subject(s) : ECL - Emitter-Coupled Logic , Emitter-Coupled Logic - ECL , Integrated Circuits , Interface Levels - ECL , Operating Voltages - ECL , -
JEDEC JESD8-9B
Abstract: This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_2 logic switching range, nominally 0 V to 2.5 V. The standard may be applied to ICs operating ...Subject(s) : 2.5 V , Logic Switching , Output Drivers , SSTL - SSTL_2 , Stub Series - Terminated Logic , Supply Voltage , -
JEDEC JESD24-2
Abstract: This addendum establishes a method for measuring power device gate charge. A gate charge test is performed by driving the device gate with a constant current and measuring the resulting gate voltage response. Constant gate ...Subject(s) : Gate Charge , Test Method - Gate Charge , -
JEDEC JESD24-12
Abstract: The purpose of this test method is to measure the thermal impedance of the IGBT (Insulated Gate Bipolar Transistor) under the specified conditions of applied voltage, current and pulse duration. The temperature sensitivity ...Subject(s) : Bipolar , Gate , Impedance , Insulated , Thermal , Transistor , -
JEDEC JESD22-B108B
Abstract: The purpose of this test is to measure the deviation of the terminals (leads or solder balls) from coplanarity at room temperature for surface-mount semiconductor devices. This test method is applicable for inspection and ... -
JEDEC JEP160
Abstract: This publication examines the LTS requirements of wafers, dice, and packaged solid-state devices. (Note: Packaging may include encapsulation, under-fill, over-mold, or other techniques to attach a die to the next level of ... -
JEDEC JESD82-7A
Abstract: This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTU32864 configurable registered buffer for DDR2 RDIMM applications. The purpose is ...Subject(s) : DDR , DDR2 , RDIMM , SSTU , SSTU32864 , -
JEDEC JESD38
Abstract: This standard is to promote unification of content and format of semiconductor device failure-analysis reports so that reports from diverse laboratories may be easily read, compared, and understood by customers. Additional ...Subject(s) : Failure Analysis - Report Format , Report Format - Failure Analysis , -
JEDEC JESD8-23
Abstract: This standard defines DC interface parameters and test conditions for a family of non-terminated CMOS digital circuits intended for use over a wide power supply voltage range. The standard bridges a number of existing JEDEC ...Subject(s) : AMB , FB DIMM , FBDIMM , FB-DIMM , Test Design , Validation Design , -
JEDEC JEP152
Abstract: This document is the work product of the JC-45.1 DDR2 DIMM Clock Skew Measurement task group.The purpose of this document is to define procedures to measure clock parameters on registered DIMMs using the DDR2 Clock Reference ...Subject(s) : Clock , DDR2 , DIMM , DRAM , Jitter , Memory , PLL , RAM , Reference Board , Registered , Skew , SRAM , Synchronous DRAM , -
JEDEC JEP106AB
Abstract: The manufacturer's identification code is defined by one or more eight (8) bit fields, each consisting of seven (7) data bits plus one (1) odd parity bit. The manufacturer's identification code as shown in Table 1, is ... -
JEDEC JESD22-B107D
Abstract: The tests mentioned herein are applicable for all package types. They are suitable for use in qualification and/or process monitor testing. The mechanical shear test (tape test) is recommended as an ongoing process monitor ... -
JEDEC JESD32
Abstract: This document provides a standard for describing an ISP device chain, opening up the possibility for third-party companies to provide value-added ISP software. The purpose of the Chain Description File is to describe the ...Subject(s) : Chain Description File , ISP Chain Device , -
JEDEC JESD22B114A
Abstract: This standard describes a nondestructive test to assess solid state device mark legibility. The specification applies only to solid state devices that contain markings, regardless of the marking method. It does not define ... -
JEDEC JESD84-C43
Abstract: This document is a mechanical product specification for a high capacity embedded memory device using the MMC interface version 4.2 and a BGA package.Subject(s) : 4.2 , BGA , embedded memory device , eMMC , high capacity , MMC ,