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JEDEC JESD8-22A

HSUL_12 LPDDR2 and LPDDR3 I/O with Optional ODT

Organization:
JEDEC - Solid State Technology Association
Year: 2012

Abstract: This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the High Speed Unterminated Logic (HSUL_12) logic switching range, nominally 0 V to 1.2 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages.
URI: https://yse.yabesh.ir/std/handle/yse/196927
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    JEDEC JESD8-22A

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contributor authorJEDEC - Solid State Technology Association
date accessioned2017-09-04T18:13:57Z
date available2017-09-04T18:13:57Z
date copyright41183
date issued2012
identifier otherHGKUAFAAAAAAAAAA.pdf
identifier urihttps://yse.yabesh.ir/std/handle/yse/196927
description abstractThis standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the High Speed Unterminated Logic (HSUL_12) logic switching range, nominally 0 V to 1.2 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages.
languageEnglish
titleJEDEC JESD8-22Anum
titleHSUL_12 LPDDR2 and LPDDR3 I/O with Optional ODTen
typestandard
page38
statusActive
treeJEDEC - Solid State Technology Association:;2012
contenttypefulltext
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