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JEDEC - Solid State Technology Association: Recent submissions
Now showing items 121-140 of 369
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JEDEC JESD8-5A.01
Abstract: This standard defines power supply voltage ranges, dc interface parameters for a high speed, low voltage family of non-terminated digital circuits driving/driven by parts of the same family. The specifications in this ...Subject(s) : Nonterminated - Digital Integrated Circuits , Normal Range - Power Supply Voltage , Power Supply Voltage - Wide Range , Wide Range - Power Supply Voltage , -
JEDEC JESD85
Abstract: This standard establishes methods for calculating failure rates in units of FITs by using data in varying degrees of detail such that results can be obtained from almost any data set. The objective is to provide a reference ...Subject(s) : Acceleration Factor , Activation Energy , Failures in Time , FITs , -
JEDEC JESD14
Abstract: Semiconductor Power Control Modules (SPCM) are modules consisting of thyristors or transistors, or both, as the primary controlling elements. Methods of manufacture of semiconductor power control modules include the ...Subject(s) : Assembling - Individual Components , Monolithic Processing Technologies , Power Control Modules , Semiconductor Power Control Modules - SPCM , -
JEDEC JESD82-27
Abstract: This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32869 registered buffer with parity for driving heavy load on high-density DDR2 ...Subject(s) : Address Parity , DDR2 , High Density , RDIMM , Register , SSTUB32869 , -
JEDEC JESD18-A
Abstract: The purpose of this standard is to provide for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users. The standard covers specifications for description of ...Subject(s) : CMOS Devices - Fast , Description - Fast CMOS TTL Compatible Logic , TTL Compatible Logic , -
JEDEC JESD24-3
Abstract: The purpose of this test method is to measure the thermal impedance of the MOSFET under the specified conditions of applied voltage, current and pulse duration. The temperature sensitivity if the forward voltage drop of ...Subject(s) : Delta Source-Drain Voltage Method , MOSFETs , Thermal Impedance Measurements - Vertical Power MOSFETs , Vertical Power MOSFETs , -
JEDEC JEP159
Abstract: The continued scaling of advanced VLSI circuits, particularly of high performance logic circuits, is driving the need for low-k materials and copper metallization in back end of the line (BEOL) interconnect systems ... -
JEDEC JESD89-3A
Abstract: This test is used to determine the terrestrial cosmic ray Soft Error Rate (SER) sensitivity of solid state volatile memory arrays and bistable logic elements (e.g. flip-flops) by measuring the error rate while the device ...Subject(s) : Accelerated , Beam , cosmic , neuton , proton , radiation , SER , Soft Error Rate , Test Method , Test Method - Beam Accelrated Soft Error Rate , -
JEDEC JESD82-26
Abstract: This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32868 registered buffer with parity test for DDR2 RDIMM applications.Subject(s) : Buffer , DDR2 , RDIMM , Register , SSTU , SSTUB , -
JEDEC JESD531
Abstract: This standard describes a test method for measuring the thermal resistance of signal and regulator diodes. The need for modification of this test method arose out of the limited description that existed earlier for both ...Subject(s) : Diodes - Signal and Regulator , Forward Voltage , Signal Diodes , Switching Method , Thermal Resistance , -
JEDEC JESD79-3-2
Abstract: The JESD79-3 document defines the DDR3 SDRAM, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments with the exception of what is stated within this addendum.
The purpose ... -
JEDEC JESD51-6
Abstract: This standard specifies the environmental conditions for determining thermal performance of an integrated circuit device in a forced convection environment when mounted on a standard thermal test board.Subject(s) : Environmental Conditions - Forced Convection , Forced Convection (Moving Air) , Test Method - Environmental Conditions , -
JEDEC JESD82-17
Abstract: This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUA32S868 and SSTUA32D868 registered buffer with parity test for DDR2 RDIMM applications.Subject(s) : DDR2 , DDR2-667 , Parity , RDIMM , Registered Buffer , SSTUA32D868 , SSTUA32S868 , Switching Parameters , Test Loading , -
JEDEC JESD28-A
Abstract: This document describes an accelerated test for measuring the hot-carrier-induced degradation of a single n-channel MOSFET using dc bias. The purpose of this document is to specify a minimum set of measurements so that ...Subject(s) : DC Stress , Hot Carrier Induced Degradation , N-Channel MOSFET , Test Method - Hot Carrier , -
JEDEC JESD55
Abstract: The purpose is to provide a standard of BiCMOS Logic series specifications for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users.Subject(s) : BiCMOS Logic Devices , Device Specification - BiCMOS Logic Devices , TTL Compatible - BiCMOS Logic Devices , -
JEDEC JESD89-1A
Abstract: This test is used to determine the Soft Error Rate (SER) of solid state volatile memory arrays and bistable logic elements (e.g. flip-flops) for errors which require no more than re-reading or re-writing to correct and as ...Subject(s) : Error Rate , Life Test , Real-Time , SER , System , Test Method - Soft Error Rate , -
JEDEC JESD22-A111A
Abstract: This evaluation procedure is written to provide USER's of ICs of small surface mount packages with a method to evaluate the capability of a component to withstand full wave solder immersion.
Typically packages capable ... -
JEDEC J-STD-020D.1
Abstract: This document identifies the classification level of nonhermetic solid-state surface mount devices (SMDs) that are sensitive to moisture-induced stress. It is used to determine what classification level should be used for ...Subject(s) : Moisture Sensitivity , Nonhermetic , Reflow , -
JEDEC JEP121A
Abstract: The purpose of this document provides the basis for the optimization of 100{}creening/stress operations and sample inspection test activities. This document is designed to assist the manufacturer in optimizing the test ...Subject(s) : MIL-STD-883 , Optimization , QCI Optimization , Screening , -
JEDEC JEP130A
Abstract: This document establishes guidelines for integrated circuit unit container and the next level (intermediate) container packing and labeling. The guidelines include tube/rail standardization, intermediate packing, date ...