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JEDEC - Solid State Technology Association: Recent submissions
Now showing items 201-220 of 369
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JEDEC JESD226
Abstract: This stress method is used to determine the effects of RF bias conditions and temperature on Power Amplifier Modules (PAMs) over time. These conditions are intended to simulate the devices' operating condition in an ... -
JEDEC JESD91A
Abstract: The method described in this document applies to all reliability mechanisms associated with electronic components.
The purpose of this standard is to provide a reference for developing acceleration models for defect-related ... -
JEDEC JEP149
Abstract: This publication applies to the application of integrated circuits and their associated packages in end use designs. It summarizes the methodology of thermal derating and the suitability of such methodologies.Subject(s) : Application , Derating , Junction Temperature , Thermal , -
JEDEC JESD82-3B
Abstract: This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV16857 14-bit SSTL_2 registered buffer for DDR DIMM applications.The purpose is to ...Subject(s) : DDR , DIMM , SSTL_2 , SSTV16857 , -
JEDEC JEP104C.01
Abstract: This publication provides a quick reference to the letter symbols and corresponding terms that are defined in JESD77-B, Terms, Definitions, and Letter Symbols for Discrete Semiconductor and Optoelectronic Devices; JESD99-A, ...Subject(s) : Letter Symbols , Memory Integrated Circuits , Microcomputers , Microprocessors , Optoelectronic , Semiconductor , Symbols - Quick Reference Guide , -
JEDEC JEP140
Abstract: The beaded thermocouple temperature measurement guideline provides a procedure to accurately and consistently measure the temperature of semiconductor packages during exposure to thermal excursions. The guideline applications ...Subject(s) : Beaded , Component Assembly , Solder Reflow Operations , Temperature Measurement , Thermocouple , -
JEDEC JESD211
Abstract: This standard is applicable to diodes that are used as voltage regulators and voltage references. It describes terms and definitions and explains methods for verifying device ratings and measuring device characteristics. ... -
JEDEC JESD8-17
Abstract: This material is intended to be reflected in supplier specifications for point to point DDR devices ranging from 400 Mb/s to 800 Mb/s operation. It is a method to specify driver impedance with something other than a number ...Subject(s) : 1.8 V , BDDR , Bi-directional , Chip Scale , CSP , DDR , Double Data Rate , DRAM , memory , RAM , SDRAM , Synchronous , -
JEDEC JESD84-C44
Abstract: JEDEC has taken the basic MMCA specification and adopted it for embedded applications, calling it "(e-MMC)". In addition to the packaging differences, (e-MMC) devices use a reduced voltage interface. These specifications ...Subject(s) : 4.4 , card , eMMC , Mechanical , MMC , multimedia , Reset Signal , -
JEDEC JESD22B113A
Abstract: The Board Level Cyclic Bend Test Method is intended to evaluate and compare the performance of SMT ICs in an accelerated test environment for handheld electronic products applications. The purpose is to standardize the ... -
JEDEC JESD84-C01
Abstract: This document is a mechanical product specification for a removable non-volatile flash memory device using the MMC interface version 4.2. The electrical specification for the MMC interface version 4.2 is document JESD84-B42.Subject(s) : MMC card mechanical removable non-volatile flash memory device using the MMC interface version 4.2 , -
JEDEC JESD65B
Abstract: This standard defines skew specifications and skew testing for standard logic devices. The purpose is to provide a standard for specifications to achieve uniformity, multiplicity of sources, elimination of confusion, and ...Subject(s) : Clock Driver , Half-period Jitter , Jitter , Lock , PLL , Skew Specification , Static Phase Offset , -
JEDEC JESD354
Abstract: GENERAL
The test set-up must be very well shielded, grounded, and securely interconnected to prevent pick-up of unwanted signals and generation of additional noise. -
JEDEC JESD9B
Abstract: This standard establishes the inspection criteria for metal and ceramic hermetic packages, individual feed throughs, and covers (lids). -
JEDEC JESD8-16A
Abstract: This standard defines the electrical parameters for high-speed interfaces for use in the 1.2V electrical environment. Included in the standard are a single ended signaling interface suitable for parallel busses, and a ...Subject(s) : 1.2 V , BIC , Bus , Interconnect , Logic , SRAM , -
JEDEC JESD207
Abstract: The normative information in this standard is intended to provide a technical design team to implement data path and control plane interface functions for an RFIC component and/or a BBIC component such that these components ...Subject(s) : Basband , BBIC , Digital Parallel , Fron End , Radio , RB-DP , RF-BB , RFIC , -
JEDEC JESD8-15A
Abstract: This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_18 logic switching range, nominally 0 V to 1.8 V. The standard may be applied to ICs operating ...Subject(s) : DDR2 Interface , I/O Interface , SSTL_18 , Stub Series , Terminated Logic , -
JEDEC JESD22-A117C
Abstract: This stress test is intended to determine the ability of an EEPROM integrated circuit or an integrated circuit with an EEPROM module (such as a microprocessor) to sustain repeated data changes without failure (program/erase ... -
JEDEC JESD22-C101E
Abstract: This new test method describes a uniform method for establishing charged-device model electrostatic discharge withstand thresholds. The charged-device-model simulates charging/discharging events that occur in production ...Subject(s) : CDM , Charged Device Model (CDM) , ESD , ESD - Charged Device Model , Test Method - Field-Induced Charged-Device Model ,