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JEDEC - Solid State Technology Association: Recent submissions
Now showing items 281-300 of 369
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JEDEC JESD230
Abstract: This document defines a standard NAND flash device interface interoperability standard that provides means for a system to be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices ... -
JEDEC JESD96A
Abstract: The normative information in this standard is intended to provide a technical design team to construct the interface on a FED and a BED such that they will operate correctly with each other (at the interface level), when ...Subject(s) : Baseband , Frequency , Front End , MAC , Phy , Radio , RF-BB , Wireless , -
JEDEC JESD208
Abstract: This document defines the Specialty DDR2-1066 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Specification is to define the ...Subject(s) : 1066 , DDR2 , DDR2-1066 , JESD79 , SDRAM , -
JEDEC JESD12-5
Abstract: This standard is intended to provide circuit designers with the information needed to develop complex integrated circuits that can be reliably and economically tested without compromising flexibility.Subject(s) : Design - Testability , Testability Guidelines , -
JEDEC JESD61A.01
Abstract: This standard describes an algorithm for the execution of the isothermal test, using computer-controlled instrumentation. The primary use of this test is for the monitoring of microelectronic metallization lines at wafer ...Subject(s) : Electromigration , Isothermal , Metallization Lines , Test , Wafer-Level , -
JEDEC JESD75-5
Abstract: This standard defines device pinout for 1-, 2- and 3-bit wide logic functions. This pinout specifically applies to the conversion of Dual-Inline-Packaged (DIP) 1-, 2- and 3-bit logic devices to SON/QFN packaged 1-, 2- and ...Subject(s) : 1-Bit , 2-Bit , 3-Bit , PACKAGE PINOUTS , QFN , SON , -
JEDEC JESD625-B
Abstract: This standard establishes the minimum requirements for Electrostatic Discharge (ESD) control methods and materials used to protect electronic devices that are susceptible to damage or degradation from electrostatic discharge ... -
JEDEC JESD24-9
Abstract: Test method to determine how long a device can survive a short circuit condition with a given drive level.Subject(s) : Short Circuit Withstand Time , Test Method - Short Circuit Withstand Time , Withstand Time - Short Circuit , -
JEDEC JESD24-1
Abstract: Describes the method of a typical oscilloscope waveform and the basic test circuit employed in the measurement of turn off loss for bipolar, IGBT and MOSFET power semiconductors. This method can be used as a standard for ...Subject(s) : Measurement - Power Device Turn-Off Switching Loss , Switching Loss , Test Method - Power Device Turn-Off Switching Loss , Turn-Off Switching Loss , -
JEDEC JEP136
Abstract: Signature Analysis is a method to reduce the number of comprehensive physical failure analyses by the application of statistical inference techniques. The purpose of this document is to promote a common definition of ...Subject(s) : Failure Analysis , Finite Population Analysis , Ongoing Process Analysis , Signature Analysis , -
JEDEC JESD75-1
Abstract: This standard establishes a 54 Ball Grid Array pinout for 16, 18 and 20-bit standard logic devices that are currently being produced in 48 and 56 Pin SSOP and TSSOP packages. The 54 Ball Grid Array Package is organized as ...Subject(s) : 54 Ball Package , Ball Grid Array , BGA , Logic Functions , Pinouts , -
JEDEC JESD82
Abstract: This specification is a reference for Registered DDR DIMM designers. JESD82 defines the physical, electrical, interface and timing requirements of a 1:10 PLL clock driver for DDR Registered DIMMs from DDR200 to DDR266 as ...Subject(s) : CDCV857 , DDR200 , DDR266 , DIMM , Double Data Rate - DDR , PLL Clock Driver , Registered DDR DIMM Applications , -
JEDEC JEP122G
Abstract: This publication provides a list of failure mechanisms and their associated activation energies or acceleration factors that may be used in making system failure rate estimations when the only available data is based on ... -
JEDEC JESD22-B111
Abstract: This Board Level Drop Test Method is intended to evaluate and compare drop performance of surface mount electronic components for handheld electronic product applications in an accelerated test environment, where excessive ...Subject(s) : Drop Test , Handheld Products , Test Method - Board Level Drop Test , -
JEDEC JESD659B
Abstract: This method establishes requirements for application of Statistical Reliability Monitoring 'SRM' technology to monitor and improve the reliability of electronic components and subassemblies. The standard also describes the ...Subject(s) : EIA-659 , Failure-Mechanism-Driven , JESD29 , Reliability Monitoring , Statistical Reliability Monitoring - SRM , -
JEDEC JESD51-7
Abstract: This fixturing further defines the environment for thermal test of packaged microelectronic devices. Its function is to provide an alternate mounting surface for the analysis of heat flow in electronic components. The ...Subject(s) : Analysis - Heat Flow , Test Board - Leaded Surface Mount , Thermal Conductivity , -
JEDEC EIA-365
Abstract: The purpose of this standard is to classify the output of solar cells for space vehicle service in accordance with requirements of EIA Format JS4-RDF4.Subject(s) : Calibration Procedure - Solar Cells , Solar Cells , Space Vehicle Service , -
JEDEC JESD51-52
Abstract: These guidelines specify testing procedures and conditions for power light-emitting diodes (power LEDs) and/or high brightness light-emitting diodes (HB LEDs) – in the following referred to as LEDs – which are ... -
JEDEC JESD76-2
Abstract: This standard defines dc interface, switching parameters and test loading for digital logic devices based on 1.2 V (normal range) power supply levels. The purpose is to provide a standard specification for uniformity, ...Subject(s) : CMOS Logic Devices , Normal Range , -
JEDEC JESD82-8.01
Abstract: This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a Â'CU877 PLL clock device for registered DDR2 DIMM applications. The purpose is to ...Subject(s) : Clock Driver , DDR2 , DDR400 , DDR533 , PC3200 , PLL ,