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JEDEC - Solid State Technology Association: Recent submissions
Now showing items 301-320 of 369
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JEDEC JESD209B
Abstract: This standard defines the Low Power Double Data Rate (LPDDR) SDRAM, including features, functionality, AC and DC characteristics, packages, and pin assignments. This scope may be expanded in future to also include other ...Subject(s) : DDR , Double Data Rate , JESD79-4 , Low Power , LPDDR , Register , SDRAM , Vendor ID , -
JEDEC JESD340
Abstract: INTRODUCTION
This standard offers an easily-measured parameter which is one of the significant characteristics in determining the stability of a transistor intended for small-signal operation. The ... -
JEDEC JESD82-19A
Abstract: This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUA32S865 and SSTUA32D865 registered buffer with parity for 2 rank by 4 or similar ...Subject(s) : DDR2. RDIMM , Registered Buffer , SSTU , SSTU32865 , SSTUA32865 , SSTUA32D865 , SSTUA32S865 , -
JEDEC JEP120-A
Abstract: This publication provides an index to terms that are defined in certain JEDEC publications. It is intended to promote the uniform use of these terms and their definitions while reducing the proliferation of new definitions ...Subject(s) : Index of Terms , Terms and Definitions - Index , -
JEDEC JEP116
Abstract: The design of ASIC circuits is becoming a significant part of system or product design, yet many problems continue to exist in current design practice. The guidelines in this document provide an explanation of common ASIC ...Subject(s) : ASIC , CMOS , Semicustom Design - ASIC , -
JEDEC JESD8-4
Abstract: This Addendum No. 4 to JEDEC Standard No. 8 defines the dc input and output specifications for a low-level, high-speed interface for integrated devices that can be a super-set of LVCMOS and LVTTL.Subject(s) : Center Tap Terminated - CTT , High Speed Interface - Digital Integrated Circuits , LVCMOS , LVTTL , -
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JEDEC JESD202
Abstract: This is an accelerated stress test method for determining sample estimates and their confidence limits of the median-time-to-failure, sigma, and early percentile of a log-Normal distribution, which are used to characterize ...Subject(s) : Accelerated Stress Test , Analysis fo Censored Data , Electromigration , Interconnect Reliability , Test Method , Time to Failure , -
JEDEC JESD15-1
Abstract: This document should be used in conjunction with the master document, JESD15, and JESD15-2, and subsidiary documents as they become available. This document is intended to function as an overview to support the effective ...Subject(s) : Compact , Compact Thermal Modeling , Component , Device , Modeling , Overview , Package , Thermal , -
JEDEC JESD69B
Abstract: This standard establishes the information required by semiconductor users from IC manufacturers and distributors in order to judge whether a semiconductor component is fit for use in their particular application. It ...Subject(s) : Information Requirements - Qualification of Silicon Devices , Qualification of Silicon Devices , -
JEDEC JESD47I
Abstract: This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.
These tests are capable of ... -
JEDEC JESD35-2
Abstract: This addendum includes test criteria to supplement JESD35. JESD35 describes procedures developed for estimating the overall integrity of thin oxides in the MOS Integrated Circuit manufacturing industry. Two test procedures ...Subject(s) : Test Criteria - Thin Dielectrics , Thin Dielectrics , Wafer-Level Testing , -
JEDEC JESD219A
Abstract: This standard defines workloads for the endurance rating and endurance verification of SSD application classes. These workloads shall be used in conjunction with the Solid State Drive (SSD) Requirements and Endurance Test ... -
JEDEC JESD77D
Abstract: Foreword
The purpose of this standard is to promote the uniform use of symbols, abbreviations, terms, and definitions throughout the semiconductor industry.
Originally developed to assist the writers ... -
JEDEC JESD33B
Abstract: This newly revised test method provides a procedure for measuring the temperature coefficient of resistance, TCR(T), of thin-film metallizations used in microelectronic circuits and devices. Procedures are also provided ...Subject(s) : Measurement - Temperature Coefficient , Metallization Lines , Temperature Coefficient - Resistance , -
JEDEC JEP143C
Abstract: This publication applies to all integrated circuits and their associated packages. The document summarizes the suite of reliability documents and publications available. These documents address reliability qualification, ... -
JEDEC JESD22-B112A
Abstract: The purpose of this test method is to measure the deviation from uniform flatness of an integrated circuit package body for the range of environmental conditions experienced during the surface-mount soldering operation.Subject(s) : High Temperature , Measurement , Methodology , Package , Test Method , Warpage , -
JEDEC JEDEC/ECA JS709A
Abstract: This standard provides terms and definitions for "low-halogen" passive and solid state devices and recommends methods for marking and labeling. This standard may be applied to all nonmetallic and nonceramic materials of ... -
JEDEC JESD22-B110B
Abstract: Component and Subassembly Mechanical Shock Test Method is intended to evaluate components in the free state and assembled to printed wiring boards for use in electrical equipment. The method is intended to determine the ... -
JEDEC JEP69-B
Abstract: This publication indicates preferred pinouts for FETs in various package designs.Subject(s) : FETs - Lead Configuration , Lead Configuration - FETs , Transistors - Field-Effect ,