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JEDEC - Solid State Technology Association: Recent submissions
Now showing items 61-80 of 369
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JEDEC JEP70C
Abstract: This publication contains a listing and description of commonly used quality and reliability related publications applicable to the semiconductor industry. It is intended to be a reference aid in finding available standards ... -
JEDEC JESD82-14A
Abstract: This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32868 registered buffer with parity test for DDR2 RDIMM applications. SSTU32S2868 ...Subject(s) : 1.8 V , Buffer , DDR2 , DDR2-800 , Parity , RDIMM , Registered , SSTU , SSTU32D868 , SSTU32S868 , -
JEDEC JESD30F
Abstract: This standard describes a systematic method for generating descriptive designators for semiconductor-device packages. The descriptive designator is intended to provide a useful communication tool, but has no implied control ... -
JEDEC JEP118
Abstract: These guidelines apply to monolithic microwave GaAs integrated circuits (MMICs) and their individual component building blocks, such as GaAs field effect transistors (FETs), resistors, and capacitors. The purpose of this ...Subject(s) : FET Life Testing , GaAs FETs , MMIC Life Testing , -
JEDEC JESD8-3A
Abstract: This Addendum No. 3 to JEDEC Standard No. 8 defines the dc input and output specifications for a low-level, high-speed interface for integrated devices.Subject(s) : Digital Integrated Circuits - High Speed Interface , Gunning Transceiver Logic - GTL , High Speed Interface - Digital Integrated Circuits , -
JEDEC JESD23
Abstract: This standard specifies a collection of procedures for testing and character designation of liquid crystal devices.Subject(s) : Character Designation - LCD , Liquid Crystal Devices - LCD , Test Method - LCD , -
JEDEC JEP154
Abstract: This document describes a method to test the electromigration (EM) susceptibility of solder bumps, including other types of bumps, such as solder capped copper pillars, used in flip-chip packages. The method is valid for ...Subject(s) : pro , -
JEDEC JESD28-1
Abstract: This addendum provides data analysis examples useful in analyzing MOSFET n-channel hot-carrier-induced degradation data. This addendum to JESD28 (Hot carrier n-channel testing standard) suggests hot-carrier data analysis ...Subject(s) : HCI , Hot Carrier , Hot Electrons , MOSFET , N-Channel , -
JEDEC JESD209-2F
Abstract: This document defines the LPDDR2 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. This standard covers the following technologies: LPDDR2-S2A, LPDDR2-S2B, ... -
JEDEC JESD8C.01
Abstract: This standard (a replacement of JEDEC Standards No. 8, 8-1, 8-1-A, and 8-A) defines dc interface parameters for a family of digital circuits operating from a power supply of nominal 3.0 V/3.3. V and driving/driven by parts ...Subject(s) : 0.3 V , 3.3 V , Digital Circuits , Integrated Circuits - Interface Levels , Interface Levels - Integrated Circuits , LVCMOS-Compatible Circuits , LVTTL-Compatible Circuits , -
JEDEC JESD8-19
Abstract: This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.8 V Pseudo Open Drain I/Os. The 1.8 V Pseudo Open Drain ...Subject(s) : DRAM , GDDR# , POD , POD18 , POD-18 , RAM , SGRAM , -
JEDEC JESD70
Abstract: The purpose is to provide a standard for 2.5 V nominal supply voltage logic devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use, thus providing compatibility ...Subject(s) : BiCmos Logic Devices , Input and Output - 5 V Tolerant , -
JEDEC JESD22-B117A
Abstract: The purpose of this test is conducted to assess the ability of solder balls to withstand mechanical shear forces that may be applied during device manufacturing, handling, test, shipment and end-use conditions. Solder ball ...Subject(s) : Failure Mode - Ball Shear , Shear , Solder , Test Method - Solder Ball Shear , -
JEDEC JESD51-51
Abstract: This document specifies thermal testing procedures for power light-emitting diodes (power LEDs) and/or high brightness light-emitting diodes (HB LEDs) – in the following referred to as LEDs – which are typically ... -
JEDEC JESD24-11
Abstract: Test method to measure the equivalent resistance of the gate to source of a power MOSFET.Subject(s) : Gate Resistance - Power MOSFET , Power MOSFET , Test Method - Gate Resistance , -
JEDEC JESD84-A441
Abstract: This document provides a comprehensive definition of the MMC/e•MMC Electrical Interface, its environment, and handling. It also provides design guidelines and defines a tool box of macro functions and algorithms ... -
JEDEC JESD8-13
Abstract: This standard defines the input, output, and termination specifications for differential signaling in the SLVS-400 environment, nominally between 0 and 400 mV. Power supplies other than the nominal 800 mV power for the ...Subject(s) : Low Power CMOS , Scalable Signaling , SLVS , -
JEDEC JESD82-10A
Abstract: This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTU32866 registered buffer with parity test for DDR2 RDIMM applications. The purpose ...Subject(s) : DDR2 , RDIMM , Registered Buffer , SSTU32866 , -
JEDEC JESD12-3
Abstract: This standard defines a minimum set of macro cell standards for CMOS gate arrays. A total of 41 macro cell types are addressed, all of which are commonly used by gate array designers to implement Application Specific ...Subject(s) : CMOS Devices - Gate Array , Gate Array , Macrocell Types ,