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JEDEC - Solid State Technology Association: Recent submissions
Now showing items 41-60 of 369
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JEDEC JESD84-B50
Abstract: This document provides a comprehensive definition of the eMMC Electrical Interface, its environment, and handling. It also provides design guidelines and defines a tool box of macro functions and algorithms intended to ... -
JEDEC JESD82-25
Abstract: This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32866 registered buffer with parity test for DDR2 RDIMM applications.Subject(s) : Buffer , DDR2 , RDIMM , Register , SSTU , SSTUB , -
JEDEC JESD8-11A.01
Abstract: This new standard provides specifications that will be used by several companies in new 1.5 V products designed in 0.12-0.15 um CMOS technologies, and in components that interface with them. The specifications allow limited ...Subject(s) : 1.5 V Interface , HSTL , Interface , LVCMOS , -
JEDEC JESD51-31
Abstract: This document specifies the appropriate modifications needed for Multi-Chip Packages to the thermal test environmental conditions specified in the JESD51 series of specifications. The data obtained from methods of this ...Subject(s) : Chop , Multi-Chip , package , Thermal , Theta-JA , -
JEDEC JESD22-B101B
Abstract: External visual inspection is an examination of the external surfaces, construction, marking, and workmanship of a finished package or component. External visual is a noninvasive and nondestructive test. It is functional ...Subject(s) : External Visual , Inspection , Test Method - External Visual , -
JEDEC EIA-397-1
Abstract: A compilation of 12 new or revised thyristor test methods which have been adopted since the original standard was issued in 1972.Subject(s) : Thyristor Test Methods , -
JEDEC JEP119A
Abstract: This document describes an algorithm for performing the Standard Wafer Level Electromigration Accelerated Test (SWEAT) method with computer controlled instrumentation. The algorithm requires a separate iterative technique ...Subject(s) : Accelerated Test , Electromigration , SWEAT , Wafer Level , -
JEDEC JESD82-6A
Abstract: This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV32852 24-bit to 48-bit SSTL_2 registered buffer for stacked DDR DIMM applications. ...Subject(s) : DDR , DIMM , Low Profile , SDRAM , SSTV32852 , Stacked , Support Logic , -
JEDEC JESD22-B115A
Abstract: This document describes a test method only; acceptance criteria and qualification requirements are not defined. This test method applies to solder ball pull force/energy testing prior to end-use attachment. Solder balls ... -
JEDEC JESD8-22A
Abstract: This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the High Speed Unterminated Logic (HSUL_12) logic switching range, nominally 0 V to 1.2 V. The ... -
JEDEC JESD22-A103D
Abstract: The test is applicable for evaluation, screening, monitoring, and/or qualification of all solid state devices.
The high temperature storage test is typically used to determine the effects of time and temperature, under ... -
JEDEC JESD92
Abstract: This document defines a constant voltage stress test procedure for characterizing time-dependent dielectric breakdown or Â"wear-outÂ" of thin gate dielectrics used in integrated circuit technologies. The test is ...Subject(s) : DIELECTRIC BREAKDOWN , GATE DIELECTRICS , TIME-DEPENDENT , ULTRA-THIN , -
JEDEC JESD50B.01
Abstract: The Maverick Product Elimination (MPE) and Outlier Management Standard was created to identify supplier requirements to improve the delivered quality and reliability of electronic components, and to develop the programs ... -
JEDEC JESD13-B
Abstract: This standard provides for uniformity, multiplicity of sources, elimination of confusion, and ease of device specifications and system design by users. It gives electrical levels and timing diagrams for B Series CMOS devices.Subject(s) : B Series - CMOS Devices , CMOS Devices - B Series , Electrical Levels - B Series CMOS Devices , Timing Diagrams - B Series CMOS Devices , -
JEDEC JESD398
Abstract: Introduction
Transistor capacitances are usually measured on two-terminal capacitance or impedance bridges. When the capacitances are in the low picofarad ranges, this two terminal measurement is not very accurate or ... -
JEDEC JESD82-20A
Abstract: This document is a core specification for a Fully Buffered DIMM (FBD) memory system. This document, along with the other core specifications, must be treated as a whole. Information critical to a Advanced Memory Buffer ...Subject(s) : Advanced memory Buffer , AMB , AMB Component Specification , DDR2 , FBD , FBDIMM , FB-DIMM , -
JEDEC JESD204B.01
Abstract: This specification describes a serialized interface between data converters and logic devices. It contains normative information to enable designers to implement devices that communicate with other devices covered by this ... -
JEDEC JESD75-2
Abstract: This standard provides a pinout standard for 16-bit wide logic devices offered in a 56-ball areagrid array package to provide for uniformity, multiplicity of sources, elimination of confusion,ease of device specification, ...Subject(s) : 16-Bit Logic , Ball Grid Array , BGA , DIP , Pinouts , VFBGA , -
JEDEC JEB15
Abstract: This bulletin explains the terminology and methods of measurement for bistable semiconductor microcircuits. It is also intended to be used with the EIA Registration Data Format for semiconductor integrated bistable logic ...Subject(s) : Letter Symbols , Quick Reference Guide , Symbols - Quick Reference Guide Data Sheet Disclaimers ,