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JEDEC - Solid State Technology Association: Recent submissions
Now showing items 21-40 of 369
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JEDEC JESD24-5
Abstract: This method describes a means for testing the ability of a power switching device to withstand avalanche breakdown.Subject(s) : Avalanche , Switching - Inductive , Test Method - Single Pulse UIS Avalanche Test , Unclamped Inductive Switching (UIS) , -
JEDEC JEP156
Abstract: This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual ...Subject(s) : chip-to-package , evaluation , identification , interaction , low-k , ultralow-k , -
JEDEC JESD435
Abstract: PREFACE
The symbols and terms of this document are contained in JEDEC Publication No. 77 and are not in conflict with those in IEC Publication 147-OC. The measurement procedures are similar to those ... -
JEDEC JESD22-A109-A
Abstract: This revised test method establishes a standard procedure for determining the effectiveness of the seal of hermetically sealed solid state devices. The objective of this revision was to modify the test parameters to reflect ...Subject(s) : Hermeticity , Test Method - Hermeticity , -
JEDEC JESD8-21A
Abstract: This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.35V Pseudo Open Drain I/Os. The 1.35V Pseudo Open Drain ... -
JEDEC JESD20
Abstract: This standard describes electrical parameters for this class of CMOS devices.Subject(s) : CMOS Devices , High-Speed - CMOS Devices , -
JEDEC JEP137B
Abstract: This publication is a companion document to the Common Flash Interface (CFI) standard, JESD68, which outlines the device and host system software interrogation handshake. JEP137 documents ID Code assignments for: 1)) the ...Subject(s) : CFI - Common Flash Interface , Identification Codes - CFI , -
JEDEC JEP142
Abstract: This document provides guidance regarding design considerations, material assessment techniques, and recommendations for material acceptance prior to use in Hybrid / MCM Products. As part of the risk assessment process, ...Subject(s) : Assessment Techniques , Design Considerations , Hybrid , MCM , Multi Chip Module , -
JEDEC JEP153
Abstract: This document provides an industry standard method for characterization and monitoring thermal stress test oven temperatures. The procedures described in this document should be used to insure thermal stress test conditions ...Subject(s) : Characterization , Monitoring , Oven Temperature , Thermal. Stress , -
JEDEC JESD79-4
Abstract: This document defines the DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of ... -
JEDEC JESD1
Abstract: This standard shows how to convert existing DIP pinouts for op-amps, comparators, and D/A converters, to chip carrier packages.Subject(s) : Chip Carrier - Leadless Pinouts , Leadless Pinouts - Chip Carriers , Linears , Pinouts , -
JEDEC JESD36
Abstract: This standard outlines the standard dc specifications, test conditions, and test loading for logic products that are designed to tolerate input and output voltages which exceed the device's power supply. More specifically ...Subject(s) : 5 V Tolerant - CMOS Devices , CMOS Logic Device - TTL Compatible - CMOS Logic Devices , Low Voltage - CMOS Logic Devices , -
JEDEC JESD82-9B
Abstract: This standard provides the functional definition, ball-out configuration and package outline, signal definitions and input/output characteristics for a 28-bit 1:2 registered driver with parity suitable for use on DDR2 ...Subject(s) : DDR2 , RDIMM , Registered Buffer , SSTU , SSTU32865 , -
JEDEC JESD79-3-1A
Abstract: The JESD79-3 document defines DDR3L SDRAM, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments with the exception of what is stated within this standard.
The purpose ... -
JEDEC JESD10
Abstract: This standard consists of a listing of letter symbols, terms, and definitions that are used in power transistors. It also includes information on JEDEC registration procedures, verification tests, and thermal characteristics.Subject(s) : Low Frequency - Power Transistors , Power Transistors - Low Frequency , Registration Procedures , Terms and Definitions - Low Frequency Power Transistors , Transistors - Thermal Characteristics , -
JEDEC JESD82-5
Abstract: This standard defines the PLL support devices required for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical ...Subject(s) : DIMM , Memory Modules , PC133 , PLL , -
JEDEC JESD24-4
Abstract: The purpose of this test method is to measure the thermal impedance of the Bipolar Transistor under the specified conditions of applied voltage, current and pulse duration. The temperature sensitivity of the base-emitter ...Subject(s) : Bipolar Transistors , Delta Base-Emitter Voltage Method , Thermal Impedance Measurements - Bipolar Transistors , -
JEDEC JESD311A
Abstract: FOREWORD
This standard describes a test method for measurement of transistor noise figure and effective input noise temperature at MF, HF, and VHF. This method is a revision of RS-311 and incorporates material ... -
JEDEC JESD82-12A
Abstract: This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTU32S869 and SSTU32D869 registered buffer with parity for driving heavy load on ...Subject(s) : 32869 , Buffer , DDR2 , Parity , RDIMM , Register , SSTL_18 , SSTU , SSTU32D869 , SSTU32S869 , -
JEDEC JESD75-3
Abstract: This standard provides a pinout standard for 8-bit logic devices offered in a 20-ball area gridarray package to provide for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ...Subject(s) : 8-Bit , Ball Grid Array , BGA , Pinout Logic ,